In the construction of integrated circuit devices, a topside or passivation film of a dielectric material is conventionally provided over the underlying layers containing the integrated circuit structure. This film, in addition to functioning as an insulation film, acts to protect the underlying structure from moisture and ion contamination that can damage or destroy the structure by causing corrosion and electrical shorts.
Silicon nitride is known as a satisfactory insulation layer for forming such a passivation film, due at least in part to its high resistance to moisture and hydrogen penetration. Moreover, the diffusivity of various impurities, such as sodium, is much lower in silicon nitride than in other insulators, such as silicon dioxide. Thus, integrated circuits made with a silicon nitride passivation layer are less susceptible to ionic contamination problems.
Recent innovations to improve complementary metal oxide semiconductor (CMOS) transistor performance have created an industry need for stressed ceramic layers compatible with current ultra-large scale integration (ULSI) techniques. In particular, channel carrier mobility for a negative metal oxide semiconductor (NMOS) transistors can be increased through introduction of tensile uniaxial or biaxial strain on a channel region of a MOS transistor. Typically, this has been accomplished by deposition of highly tensile stressed silicon nitride as a cap layer over the source/drain regions. While other novel materials may be explored for this application, silicon nitride and silicon nitride based materials are preferable due to their compatibility with existing fabrication processes.